1. Field of the Invention
The present invention relates generally to latch circuits in integrated circuits. More particularly, the present invention relates to systems and methods for detecting occurrences of soft errors that cause a latch to improperly change state, and thereby emit an incorrect data value.
2. Background Information
A technology generation in VLSI chips is defined in part by the dimensions of the average device spacing (L) between neighboring devices. With each new technology generation, L continues to decrease by about 30%, requiring a concomitant shrink in the size of devices. Together with the decrease in device size, a decrease has also occurred in the quantity of charge that is required to switch a transistor device or to retain voltage in a storage device in a circuit. For circuits that store information such as latches, static random access memory (SRAM) cells, or dynamic random access memory (DRAM) cells, the ability to retain the correct information during chip operation is paramount. For example, currently-manufactured semiconductor products are predominantly comprised of the successive 0.25 μm, 0.18 μm, and 0.13 μm technology generations. Strikingly, the amount of charge that represents a single data bit in a 0.25 μm technology generation SRAM is about sixteen times larger than that used in the 0.13 μm generation SRAM. As this trend continues, it will become necessary to improve devices and methods for sensing (“reading”), storing (“writing”), and protecting storage devices.
Even for the 0.13 μm technology generation, the amount of charge that is used to switch storage devices (switching charge) is sufficient to ensure proper reading and writing of data under normal chip operation. However, the switching charge is sufficiently low that protection of latches, SRAM, DRAM and other storage devices against corruption is a serious concern. This is in part due to the fact that several common radiation sources can produce levels of charge in excess of the switching charge. For instance, it is well known that protons, neutrons, alpha particles (a nucleus comprising two protons and two neutrons), and cosmic radiation in the ambient environment can generate significant charge in devices upon striking a VLSI chip. In materials used for manufacture of chips, such as plastics, metals and glasses, frequently there are found trace amounts of radioactive elements, which naturally occur as an embedded impurity. Such radioactive elements thus can be incorporated in the circuits or devices that comprise the VLSI chip. Upon radioactive decay, such elements may emit radiation such as alpha particles, which can produce a large track of displaced electrical charge after striking silicon in the chip. While the level of radioactive impurities can be reduced by careful monitoring of manufacturing materials, an added level of expense is required. In addition, other radiation sources are more difficult to avoid. Cosmic rays are a primary source of damaging radiation for VLSI chips, and are ubiquitous in the ambient environment. Because of their origin in the cosmos and their ability to penetrate matter, cosmic rays cannot be prevented from striking VLSI chips operating in machines located in typical office buildings, factories, homes, vehicles and other common work places.
A single strike event by cosmic radiation can readily generate a quantity of charge comparable to the current switching charge levels found in storage devices, thus rendering them susceptible to errors in retention of data. Such ‘soft errors’ do not cause permanent damage to the circuitry of the chip, but corrupt the data retained in devices, and make it necessary to re-program the device for the error to be corrected. For example, a silicon transistor inadvertently turned on by excess charge injected after radiation strike might discharge a storage node, which then would have to be re-charged.
There are several areas where data can be stored in a VLSI chip that are vulnerable to soft errors, particularly including latches that are used to retain the state of on-chip fuses. On-chip fuses are devices that can be permanently and irreversibly set, typically by destructive means where the conducting line in the fuse is broken. When the fuse is blown, it becomes non-conducting, such that the state corresponds to a logic 1. If the fuse is not blown, the logic state corresponds to logic 0. The state of each fuse can be read into a fuse latch through an output line from the fuse. FIG. 1 shows a typical latch for storing one bit of data, such as the state of an adjacent fuse. Fuse latch 1 is comprised of two coupled inverters 6 and 7, connected to fuse 2 through line 4 and load 3. The state of fuse 2 is stored at node 5 when the transistor of load 3 is turned on. For example, if latch 1 is preset so that node 5 is to equal logic 1, fuse 2 is blown, and when load 3 is turned on, node 5 takes on logic state 1. After the signal from node 5 (logic 1) enters inverter 6, it is output as logic 0 at node 8. Subsequently, if node 8 is output through inverter 7, the logic 1 value is restored at node 5. In this manner node 5 always reads logic 1 and node 8 logic 0.
To ensure that the correct latch state is preserved, accessing and setting fuse data in fuse latches can be performed during power up of the VLSI chip. During chip operation, which may continue for intervals equivalent to quadrillions of machine cycles, if a soft error were to occur in a given latch, the latch would retain an incorrect state during ongoing chip operation. Thus, soft errors generated in fuse latches during operation could remain uncorrected for quadrillions of cycles, resulting in an increased probability that latch-dependent devices or circuitry will malfunction.
One manner of addressing this problem is to design latches that are resistant or immune to switching by events such as cosmic radiation impact. Examples of related art include soft-error tolerant latches and latch circuits, which are discussed in U.S. Pat. Nos. 6,380,781 and 6,366,132. In the former reference, the geometry of the transistor in the latch circuitry is modified, including reduction of the relative size of a doped silicon source/drain (S/D) region. In this manner, it is intended that the likelihood of soft errors induced by ionizing radiation will be lessened, since it is known that a radiation strike in the S/D region results in a higher probability of creating charge that will flip the device, as opposed to the polysilicon gate region, for example. However, as is well-known to those skilled in the art, for a given circuit element size, the S/D region cannot be decreased drastically without adversely affecting device or circuit performance, so S/D regions in practical devices still will occupy a sufficient area to be susceptible to radiation. In the latter reference, examples are given where extensive additional circuitry is added to each latch to prevent a soft error from propagating to the outside circuitry of the chip. However, in many chip designs, where device density is high, it may be difficult to add such extensive circuitry for each latch. This is especially true in the case of DRAM chips.
Alternatively, the adverse impact of soft errors that occur in latches could be reduced by frequent readout of latch information, so that the period where the errors remain uncorrected is minimized. However, for fuse latches, where the state of permanently written fuse data can be accessed, frequent data readout may cause excessive current to be drawn through areas containing intact or imperfectly blown fuses. Additionally, voltage applied during read operations may alter the blown fuse properties, leading to increased error probability when accessing data. Constant read out of fuse information from the fuses into the fuse latches within the chip could also slow down chip performance. In view of the aforementioned problems, it will be appreciated that a substantial need exists for an improved method to correct for soft errors in latches.